Features
gpuemu is an operator-aware correctness regime, not a single assert. Each capability below
replaces one weak default in the field-standard torch.allclose
check — and every headline number traces to a measured study
(P1–P4).
Correctness oracle
Replace one allclose on one shape with a high-precision reference and per-op tolerances.
fp64 reference oracle
P1Every kernel output is checked against a high-precision CPU reference, per dtype.
Caught 9/9 LLM-style bugs across 5 GPU classes with 0 false positives on 15/15 controls.
Per-op calibrated tolerances
P2A p95-of-controls × 1.5 envelope fit per op and dtype, not one hand-picked atol/rtol.
Raises kernel-bug recall from 65% to 82% over a single fixed atol=1e-5, rtol=1e-2 — at zero precision cost.
Silent-bug focus
Targets wrong-output kernels that compile, run, and pass the standard check.
The bug classes torch.allclose on one shape structurally cannot see: tail-mask leaks, accumulator scale, missing normalisation, online-softmax rescale.
Adversarial input generation
Hit the partial-tile and edge cases real kernels break on, not just the happy path.
Op-schema-aware fuzzing
P3A per-op shape generator with boundary, regular, and adversarial value distributions.
Adversarial value sampling reaches 99% bug recall — +28 pp over the field-standard default oracle.
Partial-tile shape coverage
P3Deliberately generates shapes where dimensions are not multiples of the block size.
“Regular shape only” sampling misses 100% of tail-mask bugs; adversarial shapes surface them.
Reproducibility
Every failure is a seed you can replay byte-for-byte, on any machine, with or without a GPU.
Bit-identical RNG
A shared xorshift128+ generator produces the same inputs in Rust and Python.
Every flagged failure reports its seed, dtype, and shape, and reproduces byte-for-byte with gpuemu reproduce <seed>.
GPU-less validation
The correctness step compares against a CPU fp64 reference — no GPU required.
Run failing seeds on a laptop; a GPU is only needed for the optional PTX/SASS artifact step.
CI & artifacts
Gate merges on numerical correctness and hand customers a verifiable report.
Static PTX/SASS lint
P4Reads register pressure, spills, and instruction counts from compiled artifacts.
Structural Δregs predicts Δperf% across H100/A100/L40S/A10/3060 — pair it with the oracle, since semantic bugs compile to identical PTX.
One-line CI gate
gpuemu ci fuzzes, lints, and baseline-diffs, emitting SARIF for code scanning.
The in-house correctness CI that vLLM/SGLang maintainers keep rebuilding by hand, as a GitHub Action.
Signed Kernel Correctness Reports
An ed25519-signed evidence artefact customers verify offline.
An SLA-grade correctness attestation for inference-as-a-service vendors (enterprise tier).
See how the pieces fit together
These features compose into a single validation pipeline. Read the architecture walkthrough, see the P1–P4 evidence, or validate your first kernel in five minutes.
Stop shipping silently-wrong kernels
Open source, dual-licensed MIT / Apache-2.0. Validate your first kernel in five minutes — or talk to us about an enterprise pilot.